- Reduce latency within network infrastructure and trading system components using multiple high-speed hardware designs.
- Research and implement different low-latency techniques in order to identify trading system integration opportunities.
- Work to build out in-house hardware ensuring field programmable gate arrays have the ability to interface with high grade server hardware.
- Interact with third-party stakeholders.
- A Bachelor's degree within related technical field.
- ASICs design, test, and verification experience.
- VHDL, Verilog, SystemVerilog coding experience.
- 4 years minimum of C++ experience.
- Relocation Package
- Top tier high frequency trading firm
- Sign on bonus potential
- Hybrid schedule